1. Field
The present invention relates to a data holding circuit.
2. Description of the Related Art
The term “soft error” indicates an operation-restorable transient malfunction occurring at random in a semiconductor chip, which is different from a hard error that indicates permanent breakdown of a particular part of a circuit. Soft errors are caused when neutron rays generated as secondary cosmic rays, alpha rays generated from LSI materials, and the like are incident on an LSI.
Currently, there are various countermeasure methods for dealing with soft errors. The most effective and generally employed countermeasure method is adoption of such a circuit configuration that generated errors do not affect the system. For example, in an ECC (Error Correction Code) circuit, error correction can be performed relatively easily. Nevertheless, these countermeasure methods cause an increase in the chip area inapplicable to logic circuits. Thus, when the soft error rate increases with an increasing integration ratio, the problem of soft errors is expected to become more serious.
A soft error avoiding technique for a general logic circuit is described in Japanese Laid-open Patent Publication No. 2004-336123. In this method, a plurality of logic circuits are prepared so that soft errors are avoided by a majority decision logic. Nevertheless, this particular method requires several times the chip area.
Japanese Laid-open Patent Publication No. Hei 03-185921 describes a semiconductor integrated circuit provided with an output buffer in which two signals corresponding to data applied from a data storing means onto an input are applied onto individual control terminals of two pieces of first and second switching means connected in series between two power supply terminals and in which one of the switching means pieces is turned ON and the other is turned OFF so that a signal corresponding to the data is outputted to outside from a connecting middle point of the two switching means pieces, wherein the semiconductor integrated circuit is characterized by comprising a penetration current prevention circuit in which at the time of level change in the data, a control signal for bringing the two switching means pieces into an OFF state is first applied onto the individual control terminals of the two switching means pieces, and then a control signal for obtaining an output corresponding to the data is applied onto the individual control terminals.